In plain words: A chip design pairs ordinary transistors with tiny resistors that store a value as their material's resistance, letting an LSTM memory network run right next to a sensor instead of sending data elsewhere. It successfully handled a forecasting task, showing the design can do real sequence-prediction work.
Abstract
Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.
Kamilya Smagulova, Kazybek Adam, Olga Krestinskaya, Alex Pappachen James
arXiv:1806.02366 · cs.ET · submitted Jun 6, 2018
abstract · pdf
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