In plain words: A chip design that runs a long short-term memory network, which remembers past readings to forecast future ones, storing values in tiny resistors alongside standard silicon circuits. It was simulated in a common 0.18-micron chip-making process, with no accuracy or speed results reported.
Abstract · Memristive LSTM network hardware architecture for time-series predictive modeling problem
Analysis of time-series data allows to identify long-term trends and make predictions that can help to improve our lives. With the rapid development of artificial neural networks, long short-term memory (LSTM) recurrent neural network (RNN) configuration is found to be capable in dealing with time-series forecasting problems where data points are time-dependent and possess seasonality trends. Gated structure of LSTM cell and flexibility in network topology (one-to-many, many-to-one, etc.) allows to model systems with multiple input variables and control several parameters such as the size of the look-back window to make a prediction and number of time steps to be predicted. These make LSTM attractive tool over conventional methods such as autoregression models, the simple average, moving average, naive approach, ARIMA, Holt's linear trend method, Holt's Winter seasonal method, and others. In this paper, we propose a hardware implementation of LSTM network architecture for time-series forecasting problem. All simulations were performed using TSMC 0.18um CMOS technology and HP memristor model.
Kazybek Adam, Kamilya Smagulova, Alex Pappachen James
arXiv:1809.03119 · cs.ET, cs.AI, cs.CV · submitted Sep 10, 2018
abstract · pdf · html · IEEE Asia Pacific Conference on Circuits and Systems, 2018