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Wafer Quality Inspection Using Memristive LSTM, ANN, DNN and HTM (arxiv.org)
1 point by godelmachine on Sep 28, 2018 | hide | past | pdf | discuss on HN

In plain words: Tiny memory resistors that hold data without power were used to build several brain-inspired chip designs for sorting wafer defect patterns. The design with built-in memory classified best after the same training rounds while staying small and low-power.

Abstract · Wafer Quality Inspection using Memristive LSTM, ANN, DNN and HTM

The automated wafer inspection and quality control is a complex and time-consuming task, which can speed up using neuromorphic memristive architectures, as a separate inspection device or integrating directly into sensors. This paper presents the performance analysis and comparison of different neuromorphic architectures for patterned wafer quality inspection and classification. The application of non-volatile memristive devices in these architectures ensures low power consumption, small on-chip area scalability. We demonstrate that Long-Short Term Memory (LSTM) outperforms other architectures for the same number of training iterations, and has relatively low on-chip area and power consumption.

Kazybek Adam, Kamilya Smagulova, Olga Krestinskaya, Alex Pappachen James
arXiv:1809.10438 · cs.ET, cs.AI · submitted Sep 27, 2018
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