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Survey of Machine Learning Accelerators (2020 update from August 2019) (arxiv.org)
4 points by blopeur on Sep 22, 2020 | hide | past | pdf | discuss on HN

In plain words: A survey gathers publicly announced AI chips with published speed and power figures and plots them together to spot trends in power use, number precision, and training versus inference. This year's list is far larger and spans more chip designs than last year's.

Abstract · Survey of Machine Learning Accelerators

New machine learning accelerators are being announced and released each month for a variety of applications from speech recognition, video object detection, assisted driving, and many data center applications. This paper updates the survey of of AI accelerators and processors from last year's IEEE-HPEC paper. This paper collects and summarizes the current accelerators that have been publicly announced with performance and power consumption numbers. The performance and power values are plotted on a scatter graph and a number of dimensions and observations from the trends on this plot are discussed and analyzed. For instance, there are interesting trends in the plot regarding power consumption, numerical precision, and inference versus training. This year, there are many more announced accelerators that are implemented with many more architectures and technologies from vector engines, dataflow engines, neuromorphic designs, flash-based analog memory processing, and photonic-based processing.

Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, Jeremy Kepner
arXiv:2009.00993 · cs.DC, cs.LG · submitted Sep 1, 2020
abstract · pdf · html · 12 pages, 2 figures, IEEE-HPEC conference, Waltham, MA, September 21-25, 2020. arXiv admin note: text overlap with arXiv:1908.11348

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