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Supervised Learning for Coverage-Directed Test Selection (arxiv.org)
3 points by rbanffy on Jul 11, 2022 | hide | past | pdf | discuss on HN

In plain words: Instead of hand-writing constraints to steer random tests, it generates many tests and uses a learner trained on past coverage to pick those most likely to hit new logic. On an industrial chip design, this cut constraint writing and closed coverage faster than usual.

Abstract · Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification. Randomness leads to test diversity, but tests tend to repeatedly exercise the same design logic. Constraints are written (typically manually) to bias random tests towards interesting, hard-to-reach, and yet-untested logic. However, as verification progresses, most constrained random tests yield little to no effect on functional coverage. If stimuli generation consumes significantly less resources than simulation, then a better approach involves randomly generating a large number of tests, selecting the most effective subset, and only simulating that subset. In this paper, we introduce a novel method for automatic constraint extraction and test selection. This method, which we call coverage-directed test selection, is based on supervised learning from coverage feedback. Our method biases selection towards tests that have a high probability of increasing functional coverage, and prioritises them for simulation. We show how coverage-directed test selection can reduce manual constraint writing, prioritise effective tests, reduce verification resource consumption, and accelerate coverage closure on a large, real-life industrial hardware design.

Nyasha Masamba, Kerstin Eder, Tim Blackmore
arXiv:2205.08524 · cs.AR, cs.AI, cs.LG, cs.SE · submitted May 17, 2022 · updated Oct 16, 2022
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